Yasuo Naruke, executive officer, corporate executive vice president of Toshiba Corp, and president of Semiconductor & Storage Products Company, discussed Toshiba's technology strategies for NAND flash memories (the main line of its business) at a meeting that Semiconductor & Storage Products Company organized to explain its semiconductor/storage business Sept 29, 2014.
Toshiba started to mass-produce products using 15nm process technology in April 2014, planning to shift to the products during the period from 2014 to 2015. In early September 2014, it completed the construction of the clean room (for the second construction phase) in Fab 5 at its Yokkaichi Operations, which is equipped with manufacturing equipment for 15nm-process products.
After the 15nm-process products, Toshiba will shift to the BiCS (bit cost scalable) technology, which three-dimensionally stacks memory cells, instead of further scaling down the process. The company plans to start to use the BiCS for volume production in early 2016, Naruke said.
Therefore, Toshiba will considerably lag behind Samsung Electronics, which has already started volume production of 3D NAND.
"The minimum requirement for the volume production of BiCS products is a bit cost lower than that of 15nm-process products," Naruke said. "It is necessary not only to increase the number of stacked memory cell layers but also to drastically improve the throughput of etching and CVD (chemical vapor deposition) equipments.
He suggested that Toshiba aims to stack much more than 30 memory cell layers. As for the throughput, he said, "We have been developing process technologies in cooperation with multiple major equipment makers. We want to double the current throughput. It will take at least a year from now to realize that."
(Continue to the next page)