Taiwan Semiconductor Manufacturing Co has developed what it says is the foundry's first 28nm low power technology that continues the scaling trend and extends silicon oxynitride (SiON)/poly usage beyond 32nm with a dual/triple gate oxide process. This development was presented in a paper at the 2009 Symposium on VLSI Technology & Circuits in Kyoto, Japan.

Other characteristics from this technology include high density and low Vcc_min 6-T SRAM cells, low leakage transistors, conventional analog/RF/electrical fuse components and low-RC Cu-low-k interconnect.

The paper reports good 64Mb SRAM functional yield with a competitive cell size of 0.127µm2, and a raw gate density as high as 3900kGate/mm2 in this 28nm dual/triple gate oxide SoC technology. Good SRAM Vcc_min, electrical fuse, and analog performance have also been achieved, which proves the manufacturability of this technology. In addition, the paper says that low standby and low operating power transistors using SiON optimized with strain engineering and aggressive oxide thickness provide up to 25% - 40% speed improvement or 30% - 50% active power reduction over prior 45nm technology.

This technology demonstrates TSMC's ability to extend SiON/Poly as a cost-effective solution for low power and high performance.

In September 2008, the company said it was planning to deliver its 28nm process in early 2010 as a full node technology offering options of power-efficient high performance and lower power technologies. The company said it is now on track to deliver 28nm technology platforms to its customers.