Cadence Design Systems Inc has announced that Casio Computer Co Ltd has chosen the Cadence C-to-Silicon Compiler as its high-level synthesis solution. After a series of comprehensive benchmarks, Casio selected the Cadence solution over other industry products, citing the quality of results and predictability from the C-to-Silicon Compiler.
Kazuyuki Kurosawa, section manager, QV Digital Camera Division, Casio Computer Co Ltd, said: "When we analyzed the results, we determined the C-to-Silicon Compiler, combined with the other Cadence technologies, were the strongest competitive offerings in the market. We are confident these will save us development time and reduce the risk of respins."
The C-to-Silicon Compiler high-level synthesis with embedded RTL Compiler enabled Casio engineers to produce IP with smaller areas compared to the original RTL design. The combination of Incisive Enterprise Simulator (IES) with the C-to-Silicon Compiler's ability to automatically generate a SystemC wrapper for RTL verification using IES, enabled Casio to realize a seamless verification flow from SystemC to RTL.