Rambus Inc's Technical Director Steven Woo introduced a progress in the company's "Terabyte Bandwidth Initiative" in his speech at the Memory System Symposium, which took place at Meguro Gajoen in Tokyo Dec 8, 2008.
The Terabyte Bandwidth Initiative is an effort to develop elemental technologies for a memory system that can realize a bandwidth of 1 Tbyte/second between a single SoC and multiple DRAM components. Rambus will use some of the technologies derived from this effort in its "XDR 2" next-generation DRAM specifications.
Woo referred to the current state where multi-coring is increasingly applied to microprocessors, graphics processors and SoCs and explained that memory systems will consequently need further expansion in bandwidth and reduction in power consumption more than ever.
To address these circumstances, the Terabyte Bandwidth Initiative developed a technology dubbed "Fully Differential Memory Architecture (FDMA)," which pairs all command/address (C/A) lines and data lines for differential signaling. C/A lines were not used for differential signaling in the previous "XDR."
FDMA uses "32X Data Rate," a technology that enables data transmission of 16Gbps with a pair of differential signaling lines when the clock frequency is 500MHz. Through a technology called "FlexLink C/A," which uses 32X Data Rate in C/A lines, the bandwidth is further expanded by reducing the number of C/A lines and increasing the number of data lines.
Such approach becomes significant under the current circumstances, where the number of pins to address DRAM devices on the SoC side is limited, Woo said. He also introduced another technology to lower power consumption by reducing the amplitude of differential signaling lines.
Rambus is planning to commercialize its XDR 2 in or after 2010 using these elemental technologies. With XDR 2, the company will realize a bandwidth of 51.2 Gbytes/second per DRAM chip using 32 data lines and a "16X Data Rate," which allows a data transmission speed of 12.8Gbps with a pair of differential signaling lines when the clock frequency is 800MHz.
Rambus can realize a Tbyte/second class bandwidth by lining up 16 units of these chips, Woo said.