Samsung Electronics Co Ltd delivered a lecture about the development of 20nm-class DRAM at IEDM 2015 (international academic conference) Dec 9, 2015 (thesis number: 26.5).
The company said that it prototyped 20nm-class DRAM having excellent properties and claimed that 10nm-class DRAM can be realized by using the same method.
Recently, a number of engineers, etc announced that DRAM cannot be scaled beyond 20nm. DRAM stores electric charge in the capacitors inside cells and records data by allocating "1" to that state and "0" to the state of no electric charge. However, as the scaling advances and the surface area of capacitors decreases, it becomes difficult to store electric charge.
Therefore, manufactures formed long, cylindrical capacitors to increase surface area and ensure a capacity. The ratio of the diameter of the cylinder to its length (aspect ratio) is nearing 100. By the way, the aspect ratio of conventional pencils is about 22. So, the aspect ratio of the DRAM cylinder is now equivalent to that of four pencils.
According to Samsung, even though those measures were adopted, the capacity of a DRAM capacitor (Cs) in 2014 was only 52% that of a DRAM capacitor in 2009. On the other hand, etching techniques that realize a large aspect ratio have limitations, meaning that conventional measures are reaching a deadlock.
There are more problems. As the scaling advances, the parasitic capacitance (Cb) of bit lines connected to cells relatively increases in comparison with Cs, making it difficult to measure the electric charge of DRAM capacitors, Samsung said. With such reasons, it has been considered that DRAM can be scaled down only up to about 20nm.