SK Hynix Inc and Toshiba Corp prototyped a 4-Gbit STT-MRAM and announced it at IEDM 2016 (thesis number: 27.1).
Probably because it is a Gbit-class large-capacity MRAM, it drew much attention. There was a large audience, and some of them were standing.
The prototyped STT-MRAM consists of eight 512-Mbit banks. The cell area is as small as 9F2 (F: design rule), which is equivalent to that of DRAM (about 8F2). The lecturer from SK Hynix said that the cell area of conventional STT-MRAMs is 50F2.
SK Hynix and Toshiba reduced cell area, increased density and narrowed the pitch of MTJ device to 90nm. The Vdd is 1.1-1.7V, and the writing pulse width is about 30ns.
In the final phase of the lecture, they showed a picture of a 1 x 1cm 4-Gbit STT-MRAM chip. When the number of error bits was counted at the time of reading/writing data with the chip, it was a few bits after error correction, the companies said.
In addition, to prove that it properly functions, SK Hynix and Toshiba disclosed the results of reading out a 24-bit BPM-format image stored in the chip by using an FPGA. They also said that, if ECC is applied, the image will become clearer.
The two companies plan to announce the details at ISSCC 2017, which will take place in February 2017. When I asked when the STT MRAM will be commercialized, the lecturer said, "We want to commercialize it in two or three years if possible."