Canon Inc confirmed that semiconductor chips can be made with a line width of 11nm by using the "nanoimprint" next-generation semiconductor manufacturing process.
This was announced at Canon Expo 2015 Tokyo, which the company had to show its technologies from Nov 4 to 6, 2015, at Tokyo International Forum.
The nanoimprint is a technology to form circuits and elements on, for example, a silicon (Si) substrate by using a patterned "mold." With existing manufacturing processes using lithography, the minimum line width is decided by wavelength, making it difficult to continue scaling with high enough return on investment. On the other hand, the nanoimprint has no wavelength limit caused by lithography.
Canon is trying to continue scaling by commercializing the nanoimprint technology in collaboration with Toshiba Corp. This time, Canon showed a mold for the nanoimprint and a processed wafer for the first time in Japan.
Currently, Canon is testing the technology with a view to commercialization using an about 16-20nm process, planning to ship several nanoimprint devices to a semiconductor manufacturer in 2016. In general, it takes about one to one and a half years to start volume production after introducing next-generation manufacturing equipment. Therefore, semiconductor chips manufactured by using the nanoimprint technology will be shipped in 2017 if things go smoothly.
The nanoimprint technology will seemingly be applied to NAND flash memory, whose microfabrication is most advanced. When it is applied to an existing manufacturing process, the exposure process will be replaced with the nanoimprint process.
The nanoimprint process potentially slows throughput, compared with the exposure process, which can be done at once. But nanoimprint equipment is small, and multiple units can be laid out for parallel processing so that it does not become a bottleneck.
In the future, it will become possible to apply the nanoimprint technology not only to NAND flash memory but also to logic chips. However, the existing nanoimprint technology sometimes leaves dust and collapses formed patterns, making it impossible to print the pattern of the mold. So, it cannot be easily applied to logic chips. If there is one defect in an integrated circuit (IC), the entire IC becomes a defect, leading to a lower yield.
On the other hand, in the case of NAND flash memory, even when there is a defective cell, it is possible not to use the cell or use error correction, making commercialization easier.