A Japanese research group announced an SSD that combines data compression and reliability enhancement technologies at 2017 Symposia on VLSI Technology and Circuits, an international conference on semiconductor technologies, which took place in early June 2017 in Kyoto.
The research group is led by Ken Takeuchi, professor at Chuo University. In recent years, all-flash storages are being increasingly employed as high-speed enterprise storage devices. However, NAND flash memory used as a storage device has a limited number of write/erase cycles.
To overcome this disadvantage, the method of compressing data with a memory controller and writing it in NAND flash memory is drawing attention. When the amount of data is reduced through the compression, the apparent amount of data that can be written/erased increases.
The Huffman code, which is a well-known data compression technology, converts frequently-appearing data into short data (with a small number of bits) and less-frequently-appearing data into long data (with a large number of bits) so that the total amount of data can be reduced.
The technology proposed by the research group was developed by making improvements to the Huffman code to realize both compression and high reliability. Specifically, it converts frequently-appearing data into short data and writes it in a high-reliability memory state. And it converts less-frequently-appearing data into long data and writes it in a low-reliability memory state.
To realize the high-reliability memory state, the group employed methods that use only seven and six values, respectively, of the eight values of a triple-level cell (TLC). The seven- and six-value methods reduce effective memory capacity by 6.9% and 16%, respectively. On the other hand, they enable to secure a larger margin of threshold voltage and to realize a higher-reliability memory state.
Through those improvements, the group confirmed that the six-value method reduces data retention error by 92% and increases data retention time 2,900 times or more.