The cell structure of the new ReRAM
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A selector doped with boron and carbon
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Sony Semiconductor Solutions Corp developed technologies for cross point-type ReRAM whose capacity can be about 100 Gbits.

The new technologies were announced at 2017 Symposium on VLSI Technology, an international academic conference on semiconductor technologies. The company expects that the ReRAM will fill the gap between DRAM and NAND flash memory in terms of degree of integration, cost, performance, etc as a storage class memory (SCM).

This time, Sony Semiconductor Solutions developed ReRAM based on copper (Cu) ions. Its memory cell is a so-called "1S1R" type consisting of one selector and one resistive element. By employing a selector (instead of a transistor) as a selective element of memory cell, it became possible to use a cross-point type whose memory cell area is as small as 4F2. As a result, it also became possible to stack layers of memory cells and to further increase capacity.

Specifically, Sony Semiconductor Solutions developed basic technologies for large-capacity SCMs that have a writing speed of 100ns, a cycling capability of 10 million and a capacity of about 100 Gbits. And the company introduced two key technologies this time.

First, the company inserted a barrier layer between the electrolyte inside the memory cell and the Cu ion reservoir in the aim of reducing resistance variation, which is needed for increasing capacity. As a result, the mutual diffusion of materials was prevented, reducing variation.

Second, Sony Semiconductor Solutions doped the OTS (ovonic threshold switch), which is a selector inside the memory cell, with boron and carbon (BC). As a result, the company realized a low leakage current, reduction in threshold voltage variation and improvement of cycling capability, which are necessary for realizing a large-capacity cross point-type memory array.

Because of the establishment of those technologies, there is now a higher possibility that a capacity of about 100 Gbits can be realized by vertically stacking two layers of 2k x 2k cross point-type memory arrays with a size of 20nm.