Continued from Sony's Image Sensor Enables Smartphone to Take 960fps Video (1)

102Gbps bus

The size and pixel count of the CMOS image sensor is 1/2.3 inch and 21.2 million (5,520 x 3,840), respectively. With an aspect ratio of 4:3 and 16:9, 19.3- and 1.71-Mpixel images are taken, respectively. The size of each pixel is 1.22μm.

The I/F circuit supports MIPI D-PHY (2.2Gbps per lane) or MIPI C-PHY (2.0Gsps (sample per second) per lane). When 4k video is being taken at a frame rate of 30fps, the power consumption of the sensor is 424mW. Its dynamic range is 64.8dB.

Major specifications of the new sensor (source: ISSCC, created by the Sony group)

The new sensor transmits the output from the light-receiving part (PD: photo diodes) to a four-level AD (analog-to-digital) converter, digitizes it and outputs it to a "pre-processor." The pre-processor performs preprocesses such as bit formation and stores it in the DRAM via a bus.

The "main processor" connected to the bus carries out simple processes including defect correction. And the results are output to the I/F circuit via the bus.

The configuration of the sensor (source: ISSCC, created by the Sony group)

The transmission rate of the bus is 102Gbps (512 bits, 200MHz). The capacity of the DRAM is 1 Gbit (128 bits, 200MHz x 4 channels).

The image sensing part, DRAM and logic circuit part were manufactured using 90nm (1AL5Cu), 30nm (3AL1W) and 40nm (1AL6Cu) process technologies, respectively. The logic circuit part is equipped with the AD converter, pre-processor, main processor, I/F circuit, etc.

The configuration of the image sensing part is "1P4T," which uses four transistors for transmission, amplification, selection and reset, respectively, per photo diode. The transistor for transmission is formed for each pixel while the other three kinds of transistors are shared by eight pixels. This is a commonly-used configuration for applying advanced process technologies to image sensors, according to the Sony group.