The Sony group developed a CMOS image sensor chip by stacking layers including a DRAM layer and announced it at ISSCC 2017 (lecture number: 4.6).
The group (Sony Semiconductor Solutions Corp, Sony Semiconductor Manufacturing Corp and Sony LSI Design Inc) expects that the chip will be used for mobile devices such as smartphones.
In general, image sensors designed for highly-functional smartphones have a two-layered structure that uses a backside-illuminated image sensing part for the upper part and a logic circuit part for the lower part. This time, the group added a DRAM layer between the image sensing part and the logic circuit part to form a three-layered structure.
With the DRAM layer, it became possible to take images at a very high speed. For example, it is possible to take 19.3-Mpixel still images at a frame rate of 120fps and video with a pixel count of 1,920 x 1,080 at 960fps.
Without DRAM, the reading speed is determined by the data transmission speed of the interface (I/F) circuit that outputs image data to external DRAM. When DRAM is added to a chip, a large amount of data output from the logic circuit can be temporarily stored in the DRAM before it is transmitted to the I/F circuit. As a result, the reading speed is hardly affected by the transmission speed of the I/F circuit.
The Sony group has already developed a two-layered backside-illuminated image sensor whose back side is integrated with a DRAM die. And it has already been employed for digital cameras (See related article). The group considers the newly-developed sensor as a product for mobile devices for which smaller sensors are highly demanded.