Continued from Sony Unveils Manufacturing Process of DRAM-embedded Image Sensor (1)

Second, the DRAM wafer and the logic circuit wafer are joined together, and the thickness of the DRAM wafer is reduced to 3μm, which is less than 1/200 of the original thickness.

Third, the DRAM and logic circuit are electrically connected by using TSVs (through silicon vias). Fourth, the wafers of the DRAM and logic circuit are joined to the wafer of the imaging part. Lastly, it is thinned down and connected by using TSVs, forming a three-layered structure.

The thickness of the DRAM is reduced to 3μm so that the thickness of the new (three-layered) chip becomes equivalent to that of the two-layered chip consisting of the imaging part and logic circuit. The thickness of the new chip is 130μm.

About 35,000 TSVs used

The Sony group reduced the area of the I/O (input/output) part by narrowing the pitch of TSVs. In addition, the capacity of the I/O part was reduced, contributing to lowering power consumption. The numbers of TSVs connecting the imaging part and DRAM and TSVs connecting the DRAM and logic circuit are about 15,000 and about 20,000, respectively. Both of the TSVs have a diameter of 2.5μm and a pitch of 6.3μm.

At the IEDM, the Sony group disclosed the results of several reliability tests conducted by using an evaluation chip of the DRAM-embedded image sensor and stressed that there is no problem.

The size of the imaging part is 1/2.3 inch, and its pixel count is 21.2 million (5,520 x 3,840). The image sensor shoots 4:3 and 16:9 images with 19.3 million pixels and 17.1 million pixels, respectively. The pixel size is 1.22μm, and the capacity of the DRAM is 1 Gbit.

A cross-section of the DRAM-embedded chip

Original Japanese article