Samsung Electronics Co Ltd delivered a lecture on 14nm and more advanced process technologies for logic chips using FinFETs (3D transistors) at the 2013 Symposium on VLSI Technology, which took place from June 11 to 13, 2013, in Kyoto, Japan (lecture number: T7-2).
The company examined how current drive power, process uniformity and device reliability can be improved by applying a strain technology used for improving channel carrier mobility to FinFET.
For planar transistors made by using 28/20 or older process technologies, a strain technology using SiGe (silicon-germanium) source/drain is applied to pMOS. However, when this technology is applied to FinFET without changing the plane direction of Si (silicon) substrate and the shape of the SiGe source/drain, several problems occur, Samsung said.
For example, the side walls of the SiGe source/drain become planes with a high interface state density of 110, and the NBTI (negative bias temperature instability) becomes worse.
To solve such problems, Samsung compared the FinFET current drive powers, process uniformities and device reliabilities of five kinds of SiGe sources/drains with different Si substrates, channel plane directions, etc. As a result, the company found that the horizontal sigma (hΣ) type, which is made by rotating the plane direction of the conventional sigma (cΣ)-type SiGe source/drain by 90°, is the most favorable. The cΣ-type SiGe source/drain is normally used for planar transistors.
In the case of the hΣ type, a strong strain is applied to its channel. As a result, it becomes possible to increase strains in the vertical and horizontal directions by 25% and 40%, respectively, compared with a conventional structure called "conventional U Shape" (U type).
In addition, the side walls of the SiGe source/drain become "100" planes, improving NBTI. The tip of the SiGe source/drain is surrounded by "111" planes, and wet etching naturally stops at the planes, making it easy to improve process uniformity.