However, it is difficult to lower the drive voltage of an existing ferroelectric NAND to less than 3V while avoiding write disturb problems (writing data on a wrong cell). It is because, to avoid such problems, the electric potential of the bit lines connected to cells that are not selected is increased to 3V or more so that the channel electric potential of the unchosen cells is increased to diminish the difference between the electrical potentials of the unchosen cells and the word line (6V).
This time, the research group solved this problem by developing a new writing method called "Single-cell Self-boost method." It turns off two cells adjacent to the unchosen cells by applying a voltage of 1V from both ends of the bit line connected to the unchosen cells so that the channel of the unchosen cells is in the state of floating.
When the voltage of the word line is increased to 6V, the channel electrical potential of the unchosen cells increases. As a result, the difference between the electrical potentials of the unchosen cells and the word line decreases, preventing write disturb problems. The research group used this method to lower the drive voltage of a ferroelectric NAND to 1V while preventing write disturb problems.
According to the estimates of the group, the power consumption of the ferroelectric NAND capable of being driven at 1V is 86% lower than that of the existing 1.8V-driven NAND flash memory.
When an SSD is made by using the new ferroelectric NAND, it is possible to increase the number of NAND chips on which data can be written in parallel to up to 110, which is 6.9 times more than that of the existing NAND flash memory (when the upper limit of the power consumption is 1.5W). As a result, the data writing speed of the SSD reaches up to 9.5 Gbytes per second.
The research group made this announcement at the IEEE 2nd International Memory Workshop (IMW 2010), which runs from May 16 to 19, 2010, in Seoul City, Korea.