The University of Tokyo and the National Institute of Advanced Industrial Science and Technology (AIST) developed a ferroelectric NAND flash memory with an involatile page buffer.
The memory can double the writing speed of SSDs (solid state drive), they said. Also, it enables to prevent the destruction of data being written when the power supply is cut off, improving the reliability of SSDs.
Intended for SSDs used in data centers and other corporate facilities, the memory was developed by Ken Takeuchi, associate professor of the Graduate School of Engineering at the University of Tokyo, and the Frontier Device Group of Electronics Research Department at AIST (group leader: Shigeki Sakai). It will be announced at the 2009 Symposium on VLSI Circuits, which is an international conference on semiconductor circuit technologies and will run from June 16, 2009.
The ferroelectric NAND flash memory stores data by the polarization of its ferroelectric layer instead of storing electrons at a floating gate, the method used in traditional NAND flash memories. As a result, voltages needed for writing and erasing data can be reduced to 6V or less. The university and AIST aim at developing an SSD that can be rewritten 100 million times.
The random write performance of existing SSDs is deteriorated by data fragmentation. When used with servers or PCs, data as small as 512 bytes is often written to SSDs, causing data fragmentation. The performance was affected in the process of amassing fragmented pages and reconstructing them as new blocks, which takes about 100ms.
This time, a new writing algorithm called "patch write algorithm" was used to solve this problem and accelerate the random write performance twice as fast. The new algorithm starts writing data after storing write data of the page size in the page buffer, thus preventing the fragmentation of data.
In addition, the university and AIST addressed the problem that data being written is lost due to power shutdown. For this purpose, they equipped the ferroelectric NAND flash memory with the page buffer using ferroelectric transistors.
When the power supply is cut off, data being written is saved in the involatile page buffer so that it will not be lost. The number of additional transistors needed to introduce the involatile page buffer is only two per bit, increasing the chip area by less than 1%.