Toshiba Corp announced its new "SpursEngine" media processor in September 2007. The SpursEngine is a microprocessor, which redesigned Cell technologies for digital electronics and some other applications through efforts such as the addition of H.264 and MPEG-2 codec circuits to the four units of "SPE" Cell signal processors featured with it.
How was Cell DNA succeeded to the SpursEngine? Nikkei Electronics interviewed Yoshio Masubuchi, general manager of Broadband System LSI Development Center, System LSI Division, Toshiba Corp Semiconductor Company.
He was engaged in Cell architecture designing, etc, played a leader of Toshiba Cell development team at the Cell development center commonly called "STI (Sony, Toshiba, IBM) Design Center" in Austin, the US, and led the development of the SpursEngine after returning to Japan, about SpursEngine technologies (interviewer: Tomonori Shindo).
Q: The SpursEngine features four SPE units, which can be regarded as Cell's core or DNA. Can you describe the SpursEngine as a direct descendant of Cell?
Masubuchi: In the sense that SPEs are incorporated, the SpursEngine certainly inherits Cell's DNA. I, however, think it's not appropriate to call it a direct descendant of the Cell because a "PPE" CPU core, which performs general processing in the Cell, is removed.
Q: An "EIB (element interconnect bus)" high-speed ring bus can be regarded as another Cell DNA for sure along with SPEs. According to the SpursEngine release data, however, the four SPEs are apparently connected with a standard shared-bus. Did the microprocessor continue to use an EIB ring bus?
Masubuchi: The illustration wasn't perfect, I guess. Of course, the SpursEngine succeeds an EIB. High-speed buses as an EIB are very important for the utilization of SPEs.
However, compared with the Cell, which operates at nearly 4GHz frequencies, the SpursEngine operates at much lower frequencies assuming the application to digital home appliances. The sample chip operates at 1.5GHz.
To downsize the circuit area in line with the lower operating frequencies, we optimized layout design. As for SPEs in particular, we optimized layout for the SpursEngine and downsized the circuit area by 30% as we announced at the "2007 Symposium on VLSI Circuits" academic conference in June 2007.
Q: Cell employed an architecture, in which the number of SPEs can be flexibly increased or decreased, from the beginning of its design process. In the architecture, an EIB ring bus runs through the center of the chip with SPEs connected above and below the EIB. When designing the SpursEngine, did you find removing SPEs easy?
Masubuchi: Compared with other logical architectures, it is true that removing four SPEs was much easier. It can be said that the Cell design concept worked successfully. We, however, couldn't simply adopt the same Cell chip layout for the SpursEngine. That's because we had to load H.264 and MPEG-2 codec circuits in addition to SPEs on the SpursEngine. How can we locate and fit such codec circuits and four SPEs in a square chip? It required quite a bit of effort to come up with the physical layout.
Q: About the reason why the number of SPEs in the Cell was set at eight, the Cell's inventor Ken Kutaragi flatly stated that, "The Computer world is power-of-two. It's an aesthetics." What is the reason that Toshiba chose to use four SPEs for the SpursEngine?
Masubuchi: Since we developed the Cell, we have developed Cell software for diverse applications (including image recognition demonstrated at CEATEC). Through such experiences, we became able to sense how many SPEs we need in order to realize a desired application.
As the SpursEngine features logic circuits dedicated to codec processing of MPEG-2, H.264 and other encoding technologies needed for the latest AV equipment, SPEs primarily perform image recognition and tasks other than codec processing. Image recognition-related algorithm engineers naturally insisted that processing capacity is never too much, but we finally decided the number of SPEs in consideration of the balance between processing capacity and the size of a circuit area that an LSI for digital electronics can afford.
Q: In the Cell, software on the PPE sends programs to SPEs and kicks off the processing. SPEs are designed to autonomously acquire data from the main memory using DMA, yet it still appears that the PPE and SPEs interoperate.
Meanwhile, the SpursEngine employs a strategy to remove this PPE from the chip and set a host-side CPU core that plays the PPE role outside of the chip. Do the host-side CPU core and SPEs smoothly interoperate as in the Cell?
Masubuchi: It is true that conditions significantly differ whether the interoperation is closed in a chip or extends to outside of the chip, when the host-side CPU and SPEs interoperate. The SpursEngine employs PCI Express for connection with the host side, but processing efficiency will lower if SPEs frequently communicate with the external CPU.
Hence, the SpursEngine integrated the "Control Processor" dedicated CPU core on the chip for smoother interoperation between SPEs and the host side. The Control Processor is Toshiba's proprietary 32-bit CPU core. It doesn't perform as much processing as a PPE does, but it supports the interoperation standing between the host outside of the chip and SPEs. We made it unnecessary for SpursEngine users to touch this Control Processor's firmware.
Q: How do software on the host side make access to the SpursEngine?
Masubuchi: The host side makes access using a dedicated device driver. As for host environments, we currently provide a driver for Windows PCs that operate with an 86 microprocessor. We are planning to consider offering device drivers for Linux, etc.
Q: Toshiba displayed a panel of a SpursEngine II roadmap at CEATEC. Has the development already begun?
Masubuchi: Toshiba is just discussing the SpursEngine II now. We have just completed a SpursEngine prototype LSI and are currently advancing works to start shipping a mass-produced sample LSI in the first half of 2008.