The latest prototype chip (development code: DD2) die
The latest prototype chip (development code: DD2) die
[Click to enlarge image]

Sony Computer Entertainment Inc. (SCE) has finally revealed the next-generation PlayStation 3 (PS3) game console. While reading the company's press release, some interesting numbers caught my attention. One of them is 3.2 GHz, the operating frequency of the Cell microprocessor used in the PS3. When the Cell processor was announced at the ISSCC 2005 event in February, 2005, SCE said, "The prototype chip operates at 4 GHz and higher frequencies, but we have not yet determined the operating frequency of the mass-produced chip." The company seems to have concluded that 3.2 GHz is most appropriate considering such factors as yields and power consumption.

What came as a surprise was the number of signal processor elements (SPE) contained in the Cell processor were reduced from eight to seven in the game console specifications. The number of SPEs had previously been boosted to eight from the original six determined by Cell developers during the design process, because Ken Kutaragi, President of SCE and Group CEO, insisted on using exponential numbers based on his belief that, "This is an aesthetic." There must have been a good reason for reducing the number of SPEs.

When I directly asked what the reason was, SCE answered, "We made the decision in view of production yields." Eight SPEs account for more than half of the total surface area of a chip. In addition, it is easier to estimate a critical path because each core features high-speed operational 256 KB SRAM. It must have been very difficult at this moment to enable all eight SPEs to operate at the targeted frequency and power supply voltage. Even if the number of SPEs had been unchanged at six, SCE might have had to reduce it to five in the PS3 specifications after all. In this respect, Kutaragi's persistence to use eight SPEs may have been correct.

Hiroki Eda, Nikkei Electronics