The Sony group (Sony Semiconductor Solutions Corp and Sony Semiconductor Manufacturing Corp) made an announcement about the manufacturing process of a CMOS image sensor that is made by stacking layers including a DRAM layer and making them into a chip at IEDM 2017.
The image sensor was first announced at ISSCC 2017 and has already been employed for smartphones (See related article). But this is the first time that the group has unveiled the manufacturing process.
Image sensors designed for highly-functional smartphones usually have a two-layered structure consisting of (1) a backside-illumination imaging part (upper layer) and (2) logic circuit part (lower layer). This time, the Sony group inserted a DRAM layer between the imaging part and the logic circuit part, forming a three-layered structure. In other words, from the top, the layers are the imaging part, DRAM and logic circuit part.
The DRAM layer enables to shoot images at a very fast speed. For example, the image sensor announced at ISSCC 2017 was capable of shooting 1,920 x 1,080-pixel video at a frame rate of 960fps.
DRAM thickness reduced to 3 micrometers
The overview of the manufacturing process of the DRAM-embedded chip is as follows. First, the imaging part, DRAM and logic circuit are formed on different silicon (Si) wafers, respectively. The imaging part, DRAM and logic circuit are made by using 90nm, 30nm and 40nm manufacturing processes, respectively.